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Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor | IEEE Journals & Magazine | IEEE Xplore

Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor


Abstract:

The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to i...Show More

Abstract:

The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to increase the compute density of high-volume commodity 2P/4P blade servers while operating within the same power envelope as earlier-generation AMD Opteron processors. A key enabling feature, the probe filter, reduces both the bandwidth overhead of traditional broadcast-based coherence and memory latency.
Published in: IEEE Micro ( Volume: 30, Issue: 2, March-April 2010)
Page(s): 16 - 29
Date of Publication: 12 April 2010

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