High density 3D, CMOS circuits with ELO SOI technology

A priori crystalline silicon-on-insulator-on-silicon structures were fabricated with 8 masks. With this three-dimensional CMOS technology, three high-quality transistor channels are stacked vertically. Dual-gate PMOS transistors on top of NMOS transistors deliver the same current for the same channel width. 3D CMOS test circuits have been built with a footprint of one third of their 2D bulk counterparts.