Buried stacked capacitor cells for 16M and 64M DRAMS

The technology and performance of two trench capacitor cell variants for 16 & 64M DRAM application are assessed. Critical cell leakage mechanisms are determined and means of reducing them further are compared. Trench-transistor separation is shown to be non critical with regard to transistor performance and double channelstop implant technology also allows for further transistor optimisation possibilities.