Field isolation and active devices for 16 Mbit DRAMs

Results are presented showing that conventional LOCOS Isolation can be used for memory cells with pitches less than 1.5μm. Careful tuning of LOCOS overetch and channel stop implantation as well as optimization of the cell transistor yield satisfactory isolation of 0.7μm LOCOS and half-micron active devices with active area widths of 0.25μm.