Interconnects for ULSI: State of the Art and Future Trends

State of the art 0.35 μm generation makes to a large extent use of basic steps developed in previous 0.5 μm generation: Physical Vapor Deposition (PVD) for adhesion/barrier layers and Al interconnects, Chemical Vapor Deposition (CVD) W for contacts and vias; on the other hand, for interlevel dielectric, it tends to use new High Density Plasma (HDP) deposition with improved gap-filling capability, in conjunction with global planarization by Chemical Mechanical Polishing (CMP), to afford limited depth of focus in optical lithography, and increasing number of interconnect levels. Further down scaling will lead to severe limitations in terms of RC interconnect delay and reliability. The overall trend is to keep nearly constant the vertical dimensions, which results in ever increasing aspect-ratio for contact/via holes, and metal lines; it places requirements for a general use of CVD deposition which offers a nearly 100% step coverage. Alternative Multilevel Metallization Systems (MLM's) will be considered DAMASCENE architecture highly promising to handle high aspect-ratio metal lines, and borderless contacts and vias, to reach the ultimate interconnect density. Low dielectric constant polymers and Cu metallization, promise to play a major role in performance improvement, at the expense of a significantly more complex integration. In addition to a resistivity lower than Al, Cu should provide improved reliability. Importantly, fringing (interline) capacitance tends to play a more important role compared to interlevel capacitance below 0.35 μm; combining low resistivity Cu with low permittivity dielectrics, could reduce RC delay by a factor of 4.