A CAD tool for the optimization of video signal processor architectures

This paper presents a system level design methodology and its implementation in a CAD tool for the optimization of video signal processor (VSP) architectures. These VSPs, consisting of dedicated as well as programmable modules, are highly suitable for performing composite schemes of image processing algorithms under real time constraints, whereas the optimization aims at the most suitable combination of dedicated and programmable modules for the overall system. Nevertheless, in order to apply optimization techniques, it is mandatory to estimate a set of performance measures like execution time and area expense for each module in advance. Based on these performance measures estimated for a finite set of dedicated and programmable modules, the optimization can be carried out. By using mixed integer linear programming as the optimization framework, VSP architectures can be derived, being optimal in terms of chip area and throughput rate.