Suppression of the Vt Roll-Up Effect in Sub-Micron NMOST

Anomalous increase in Vts (NMOS Vt roll-up effect) with the decreasing gate length in sub-micron technologies is usually attributed to the lateral redistribution of doping near source and drain junctions, or to silicon interstitial capture in gate oxide. Our results demonstrate that the poly-Si gate doping level dominates the observed Vt rollup effect and suggest a simple method for its suppression.