A 0.25μm Fully Planarized CMOS Technology

CMOS devices with 0.25μm physical gate lengths were fabricated on 200mm wafers utilizing a twin well, double level metal, fully planarized process. Single work function n
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poly silicon was chosen as the gate electrode for its ease of manufacturability. Deep UV lithography was used to define the critical layers; Poly, Contacts, Metal 1, Vias and Metal 2. All other levels were exposed using i-line lithography. It was necessary to utilize fully planarized CMP dielectrics due to reduced depth of focus inherent in DUV lithography. Due to reliability considerations 2.5V was the targeted power supply voltage. Electrical and process data is presented.