New Transient Characterization of Latchup Phenomenon in CMOS Cell

This paper presents an analysis of the latchup development in CMOS integrated circuits. It sets out the time resolution of the triggering relevant to the different elements involved in the mechanism. So, the importance of the external excitation pulse duration for the triggering process is pointed out and quantified. Based on a lumped element model, the latchup switching current measured at the terminal is completely characterized as a function of the pulse characteristics. An original analytic transient latchup criterion is proposed. Experiments carried out on test structures fabricated in 2 μm, epitaxial, industrial technology as well as SEM observations confirm the validity of the criterion.