RF performance upgrading of low-power 40nm-node CMOS devices by extremely low-resistance partially-thickened local (PTL)-interconnects

A new partially-thickened local (PTL)-interconnect structure with an extremely low resistance is developed for the 40 nm-node low-power CMOS device to boost the RF performance. The PTL-interconnect is featured by the Cu dual-damascene (DD) interconnect combined with the slit-contact (SLICT) in the low-k pre-metal-dielectrics (PMD, k=3.1), accomplishing 50% reduction in the resistance of metal-1 (M1), and the contact resistance between M1 and the gate silicide-interconnect also decreased remarkably. The maximum oscillation frequency (f
_max
), which is influenced strongly by the effective gate resistance as an input signal port, increased 30% referred to that with conventional W-pillar contacts in the SiO
₂
-PMD. The low-resistance PTL-interconnect backed with the Cu-DD SLICT in the low-k PMD is essential for low-power RF/mixed-signal SoCs.