A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels

A front-end IC for EPR-IV partial-response maximum likelihood (PRML) detection systems used in magnetic recording systems is developed. Reorganization of the front-end architecture reduces clock acquisition time and lowers chip complexity and power. A new six-pole 80-MHz continuous-time filter equalizes waveforms to the desired ERR-IV target. The equalizer is tuned in quality-factor and frequency to a synthesized system clock, reducing drifts due to processing and temperature variations. An on-chip timing recovery circuit, incorporating a 160-MHz sampled-analog phase detector and 200-MHz voltage-controlled oscillator (VCO) regenerates the data clock. The phase detector used is appropriate for (1, 7) code, and can be extended to operate on (0, k) codes. During head seeks, a secondary loop incorporating the VCO locks to the write clock and acquires the anticipated read-clock frequency. All signal paths are serial and fully differential. The chip is fabricated in a 1-/spl mu/m CMOS process.