SRAM Core Modeling Methodology for Efficient Power Delivery Analysis

It is common that high performance integrated circuit today achieves faster processing speed by padding as many memory cells or SRAM (Static Random Access memory) in its core logic as possible [1]. The build-in SRAM cell allows the PCH (Platform Controller Hub) to access the nearest data storage with least latency. While the SRAM cells are aggressively populating the PCH core, the total chip power consumption is increasing. Power gating technology becomes a juicy implementation on these SRAM to turn off the power when it is not in used. In this project, the computing power savings have achieved ∼900mW and proven to be a good strategy for preserving mobile computing power and extension of battery life span. However, the aggressive implementation of power gating and un-gating technology, if not understood fully, will be leading to uncontrollable transient ac noise on the power delivery network (PDN) and ultimately impacting the PCH core performance.