Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories

This paper proposes circuit technologies adaptable to the potential scalability of flash memory cells and an accurate internal voltage generator for use under low voltage operation. A circuit with a relaxed layout pitch, bit-line clamped sensing multiplex, and intermittent burst data transfer (four phases with 500 ns/20 ns) is proposed for a three times feature-size pitch. A 5-/spl mu/A low-power dynamic band-gap generator with voltage boosted by using triple-well bipolar transistors and voltage-doubler charge pumping, for accurate generation of 10 to 20 V, are also proposed for use at V/sub vv/ of under 2.5 V. To demonstrate the circuit feasibility, a 105.9-mm/sup 2/ 128-Mb experimental chip was fabricated using 0.25-/spl mu/m technology.