Wave pipelines via look-up tables

Look-up tables (LUTs) allow the delay of digital blocks with different types of gates or different logic depth to be equalized; thus, they could be a useful building block for the construction of wave pipelined circuits. In this paper, this alternative is explored by using a RAM-based FPGA. An experimental LUT-based wave pipeline 7-bit array multiplier has been constructed. The main results, for an intentionally skewed clock synchronization strategy, show that it is possible to obtain throughputs as high as 80 MHz with 8 waves running in a 13-LUT logic depth combinational circuit. The prototype presents a continuous range of frequency operation and exhibits an acceptable dependence with power supply variations. In terms of fast-prototyping, wave pipelining on FPGAs allows the designers to obtain a unique combination of high-throughput and minimum-latency.