Design of signature registers for double error bit identification

Design techniques for Signature Analysis Registers (SARs) and Multiple Input Signature Registers (MISRs) are presented along with algorithms which facilitate the identification of all single and double errors in faulty circuit output responses. The hardware area overhead associated with this approach is less than that of previous error bit identification techniques. The applications for which this technique is best suited include Built-In Self-Test (BIST) with fault diagnosis capabilities for memories and other regular structures.