Bus architecture for low-power VLSI digital circuits

One of the most important issues in modern VLSI circuits design is the power reduction. Many approaches to resolve this problem are proposed in literature, most of them using a nonconventional technology. This work proposes a new architecture which reduces the power consumption in the interconnection busses into the chip reducing the voltage swing and uses the conventional technology. Because the dissipation on these busses can reach 50% of the total power dissipated in a VLSI chip, this approach, which can theoretically reach very high values of power reduction on the bus, is very promising. An experimental chip is also designed to monitor the noise problems.