A fundamental basis for power-reduction in VLSI circuits

Presented in this paper is a fundamental mathematical basis for power-reduction in VLSI systems. This basis is employed to (1) derive lower bounds on the power dissipation in digital systems and (2) unify existing power-reduction techniques under a common framework. The proposed basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/sec. Different architectures implementing a given algorithm are equivalent to different communication networks each with a certain capacity C (also in bits/sec). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. Numerical calculations for a simple static CMOS circuit and fundamental basis for the power-reduction capabilities of parallel processing and pipelining are presented.