Development and characterisation of high electrical performances TSV for 3D applications

Today, a new trend in wafer level packaging is to add more than one die in the same package and, sometimes, to use the third dimension in order to: Decrease the form factor of the final system; Improve the thermal and electrical performances of the device; Decrease the cost of the final product. In order to stack the heterogeneous components in the third dimension, TSV (through silicon vias) is a very promising technology compare to wire bonding. In this paper, the technological bricks specifically developed for 3D integration demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer. This flow needed to develop specific wafer level packaging technologies such as: Top chip & bottom chip interconnections; High aspect ratio TSV included into the bottom wafer; Backside interconnections for subsequent packaging step; Temporary bonding and debonding of bottom wafer. Top chip stacking on bottom wafer In the first part of the paper, the complete process flow will be presented. Then, a technical focus will be done on the specific steps developed for the improvement of the TSV's electrical performances. Finally, the electrical results achieved on a specific test vehicle, similar to the demonstrator will be discussed. The electrical results obtained on a technological test vehicle will be firtly presented. Those results include electrical continuity, pillars resistance, TSV resistance and capacitance and TSV insulation and current losses. Then, the electrical results obtained with the ¿high electrical performances¿ process on the functionnal demonstrator will be showed, including a specific focus on the TSV capacitance measurements.