SiC power semiconductors in HEVs: Influence of junction temperature on power density, chip utilization and efficiency

With SiC, junction temperatures of power semiconductors of more than 700?C are theoretically possible due to the low intrinsic charge carrier concentration of SiC. Hence, a lot of research on package configurations for power semiconductor operation above 175?C is currently carried out, especially within the automotive industry due to the possible high ambient temperatures occurring in hybrid electric vehicles (HEVs). This paper shows, that a higher junction temperature though does not necessarily guarantee a higher utilization of the SiC chips with respect to the current that the device can conduct without overheating. The reason is, that for most power devices the power losses start to increase very rapidly at high junction temperatures while the power that can be dissipated always increases linearly with the junction temperature. The junction temperature, where the device current starts to decrease at, is derived for different SiC chips using measured onstate conduction and switching losses in this paper. This paper furthermore analyzes in detail, how the junction temperature on the one hand is influenced by boundary conditions and on the other hand influences itself the core parameters of a converter such as efficiency, the required chip area (i. e. cost) as well as the volumetric power density and thus forms an additional degree of freedom in the design of a power electronic converter. While calculating the optimum junction temperature and analyzing its impact on the system performance, it is demonstrated, how these results can help to find the best suited power semiconductor device for the particular application. The performance of the calculations is shown on a design applied to a drive inverter for hybrid electric vehicles with normally-off SiC JFETs. Operated close to the optimum junction temperature of the SiC JFETs, it reaches a power density of 51 kW/l for the power modules and the air-cooling system, which is shown to be doubled by increasing chip size and using an advanced power semiconductor package with a lower thermal resistance from junction to ambient than the for this case assumed 1 K/W.