FPGA implementation of a digital FM modem for SDR architecture

FPGA implementation of a high-performance programmable digital FM modem which is appropriate for inclusion in software-defined radio (SDR) architecture. The proposed design consists of reprogrammable, area-optimized and low-power features. The modulator and demodulator contain a compressed direct digital synthesizer (DDS) for generating the carrier frequency with spurious free dynamic range (SFDR) of more than 70 dB. The demodulator has been implemented based on the digital phase locked loop (DPLL) technique. The proposed FM modem has been implemented and tested using Virtex2Pro university board as a target device. The FPGA implementation of the FM modem can operate at a maximum frequency of 104 MHz, involving around 8.4 K equivalent gates in the XC2VP30-7ff896 FPGA device and consuming about 130 mW power.