The electronics in the detector head of the AGIPD detector — A 1MPixel, 5MHz camera for the European XFEL

The European free electron laser (XFEL) will provide trains of 12.4 keV X-ray photons. With a repetition frequency of 10 Hz 0.6ms long trains with 3000 bunches will be generated with a bunch to bunch separation of 200 ns. For experiments at XFEL the AGIPD consortium is developing a 2-dimensional 1Mega pixel detector to record individual pictures for bunches separated by 200 ns. As a first step ¿200 pictures per train will be stored as analogue values in capacitors inside ASIC's. To minimize charge leakage a fast digitization system will be developed as a board level electronic system housed in the detector head. In the baseline design it will handle up to 400 pictures/train. 1024 ADC's each with 50 MS/s and 14 bit will be mounted in 16 modules and generate a data rate of 16 × 51 Gbit/s into 16 FPGA's, one per module. After correction and pre-sorting the data of each module will be sent on a standard IT 10 Gb/s fibre link to the backend system. IP protocols are targeted for use in data transfer and VHDL code for the VIRTEX-5 FPGA has been implemented. Performance tests show that 99% payload link occupancy can be achieved, well above the required 55%. Control of the detector head and it's synchronization will be performed using dedicated differential signal lines passing clock and event signals between the accelerator timing system receiver and control master and the detector head FPGA's. Slow control and train synchronous information exchange (100 ms) will be implemented using reliable TCP/IP Ethernet with the messages passed between detector head microcontrollers and the control master. The basic building blocks required have been investigated with evaluation boards and in-house developments.