A modular high speed data acquisition system for PHENIX TEC/TRD front end electronics

The TEC/TRD detector front end electronics is responsible for reading out more than 21 thousand channels from the PHENIX central arm. To optimize the response of the electronics for the detector signals, several operating parameters in the front end readout chain can be altered. Although it's possible to perform this task in the experiment data acquisition and control itself, this is better accomplished using a mock-up of the system in a controlled environment, which can also be used to simplify the maintenance of the hardware. The TEC/TRD front end electronics communicates with the data acquisition back end using 1 Gbit/s optical links. For a test setup, a dedicated hardware is needed to read out and process the information coming out from each link. For this purpose, a compact data acquisition system capable of reading a small number of channels was design using commodity hardware and communication protocols. The ¿glue logic¿ blocks in the system are implemented inside FPGAs, while most of the processing and interfacing tasks are done by dedicated devices. The design supports either a 16 bit microcontroller (Microchip DSPIC33) or a high performance 32 bit device (ARM9 core), which provides the necessary support for the implementation of high level communication protocols and some data processing capability. A 10/100 Ethernet interface allows the microcontroller to implement an HTTP server on board, providing a simple user interface to the system, while a High Speed USB interface is used to transfer the data to a computer. As each front end readout board is highly configurable, a slow control and monitoring support hardware was built using the CANBUS protocol. Several stages of data buffering and storage memory are available, which makes possible to perform some simple operations on the data, combining the flexibility of the microcontroller with a direct ¿in hardware¿ data processing implementation in the FPGAs.