PADI-2,-3 and -4: The second iteration of the fast Preamplifier — Discriminator ASIC for Time-of-Flight measurements at CBM

Within the European project JRA-12, we have designed a general purpose PreAmplifier-DIscriminator (PADI) ASIC to be used as Front-End-Electronics (FEE) for the readout of timing Resistive-Plate Chambers (RPC) in the CBM experiment at FAIR. These fast timing detectors deliver signals with rise times t
R
<500 ps and generate a prompt charge usually in the range of 30 to 2000 fC [1]. Time resolution of σ
tD
<50 ps can be reached provided the preamplifier-discriminator stage has an intrinsic electronic resolution of σ
tE
<15 ps [2]. The first prototype developed was PADI-1, a three-channel ASIC in 0.18 μm CMOS technology [3]. The subsequent versions PADI-2 to -4 [3] have been changed from voltage to current biasing, which leads to an increase of the crosstalk rejection ratio at chip level, of more then 20 dB. PADI-2 and PADI-3 have different LVDS output levels, since they will be connected to a High Resolution TDC chip for digitization which is currently under development (GET4) [5] requiring LVDS input signals. On all chips the number of channels has been increased to four and an OR feature allows to daisy-chain chips for trigger purpose. PADI-4 finally was developed for diamond timing detectors. In this article we present the results of comparative measurements with all these prototypes and define the ideas and goals for a next iteration.