Timing generator using dual delay-locked loop

In this paper, the new architecture of a timing generator using dual delay-locked loop (DLL) is proposed. With the aid of coarse and fine tuning mechanisms, the timing generator can provide sub-gate resolution with precise close-loop control and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.35 ¿m 2P4M technology. The chip area occupies 1.36 mm
²
. It can interpolate the reference clock cycle with 80 divisions to obtain 45 ps resolution when running at 280 MHz. The DNL and INL are within -0.3~+0.6 and -0.8~+0.4 LSB, respectively.