Hardware implementation of an SVD based MIMO OFDM channel estimator

This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm
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design. This corresponds to ∼30 M estimates per second, which is more than needed in current wireless systems. Further, simulations show that this design would consume an average power of around 8.5 mW with a peak power at 14.2 mW. The presented data shows that it is possible to use these kind of advanced channel estimation strategies in wireless receivers, even though there has been no prior reports of these being implemented.