Comparator-based successive folding ADC

A 4-bit 1-GS/s ADC with a comparator-based successive folding (CSF) architecture is presented. Residue pre-charging and successive folding techniques are proposed for the CSF ADC to enhance quantization speed and achieve less complexity, leading to high power efficiency. Simulation results show that the ADC obtains a SNDR of 23.7 dB at Nyquist input frequency and consumes 430 ¿W from a 1 V supply in 65 nm CMOS, yielding a FOM of 34 fJ per conversion step.