Design Considerations for the Chain Magnetic Storage Array

A computer storage design using the chain store device as both a DRO and an NDRO storage element is discussed for an array organization of one megabit capacity and 500-nsec cycle time. The bit/sense system and schemes for minimizing the longitudinal fields inside the array during the “write” portion of the cycle are presented. Noise due to difference in the information states of the device is studied experimentally and through evaluations of computer solutions of simulated bit/sense lines. The word-line characteristic impedance and its dependence on the magnetic behavior of the device during the “read” portion of the cycle and on the sending and receiving end terminations are examined with consideration given to long word lines. Sources of noise and bit-to-bit interaction are discussed and comparisons between calculated and experimental results obtained from a small model of the array are given.