Design and Development of an Ultralow-Capacitance, High-Performance Pedestal Transistor

High-performance transistors with small geometries require a highly doped collector region to produce a large impurity gradient at the collector-base junction. This allows the structure to sustain high current densities and to attain low collector series resistance. However, the resulting increase in collector transition capacitance degrades the ac characteristics of the transistors. A structure is proposed and experimental results are presented in this paper to demonstrate that the conflicting requirements above, which limit the high-performance characteristics of transistors, can be resolved by the planar IC process.