Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

As traditional CMOS scaling becomes progressively more difficult and less beneficial to overall system performance, three-dimensional silicon integration technologies have begun to receive considerable attention. An advanced packaging solution based on a thin silicon carrier has been developed to provide interconnection between integrated circuits (ICs) and other devices at densities far beyond those of current first-level packaging. The silicon carrier employs fine-pitch Cu damascene wiring, high-density solder interconnections, and through-silicon vias (TSVs). A key enabling technology element is the TSV, which may be naturally scaled to provide vertical interconnection in stacked ICs as well as silicon carriers. In this paper, we discuss the evolution in both TSV design and process flow that has led to TSV technology which produces vias with resistances on the order of 10–20 mΩ and yields on the order of 99.99% at wafer level in a research laboratory environment. Two generalized process approaches to forming TSVs are discussed, the “vias-first” and the “vias-last” methods, along with related advantages and potential drawbacks of each. Improvement to these process flows and structures is afforded by simple changes of via geometry from cylindrical to annular or from annular to multibar. While various TSV metallurgies are reviewed, tungsten is shown to be a nearly optimal choice. Results on via resistance, electrical yield, and current-carrying capacity are covered. The use of electrical modeling to predict structures with superior electrical and mechanical properties is also described.