Analysis and design of an interleaved series input parallel output ZVS forward converter

A novel interleaved series input parallel output ZVS forward converter (ISIPO ZVSFC) is proposed in this paper. The series input and parallel output architecture enables the converter cells to share the input voltage and output current equally. The interleaved operation diminishes the output current ripple in the output capacitor. That reduces the size of the output filter. By using active-clamp circuit and resonant circuit, the converter can achieve ZVS operation for all the main and auxiliary switches. The active-clamp circuit is also used to reset the energy stored in the leakage inductor to minimize the voltage spike on switching devices. All these features make the proposed converter suitable for dc-dc converters with high input voltage, high output current, high power and high efficiency applications. An experimental prototype with 400 V input and 24 V/480 W output is built to verify the theoretical analysis and the performance.