Design challenges for a high performance HSDPA RF transceiver IC

A tri-band (bands I, II, V/VIII) single-chip RFIC has been designed in 0.18 ¿m SiGe BiCMOS process to meet HSDPA Category 8 requirements. Competitive radio RF performance necessitates optimum tradeoff of design challenges. The transceiver relies on front-end SAW filters for increased system performance margins. Calibration schemes for receive DC offset, transmit carrier leakage, and VCO frequency stability are implemented on-chip to minimize related impairments. The direct-conversion receiver achieves 3-4 dB margin on reference sensitivity and >12 dB margin on all adjacent channel and in-band blocking cases. The direct-modulation transmitter achieves more than 90 dB dynamic range and excellent EVM (3.0%) and ACLR (-48 dBc) performance over the top 11 dB of power range. In Band I, the RX and TX sections draw each 35 mA and 65 mA, respectively. Two dedicated on-chip fast-settling fractional-N synthesizers provide LOs for both RX and TX. The chip is housed in a 5 × 5 mm
²
81-pin VFBGA package.