Design of a 1.0 /spl mu/m reconfigurable VLSI CMOS fuzzy processor which runs at 100-50 MFIPS with an active rule selector

A trigger system in high-energy physics experiments (HEPE) has to decide, in few /spl mu/s, if the data related to a nuclear event have to be stored or not. Normally, these data, are composed of a bit map where the track coordinates are stored. The possibility to use a suitable fuzzy processor for HEPE has been investigated and the simulations show that a fast fuzzy processor can solve, in many cases, the trigger problem. A 4-input 50 mega fuzzy inference per second (MFIPS) fuzzy processor has been fabricated in VLSI 1.0 /spl mu/m CMOS technology using the Cadence CAD we got by Eurochip. This processor has been tested and it works properly. It is a first release of the final high-speed processor that will be composed of a preprocessor unit and a high speed processor core. The preprocessor is designed to reject the nonactive rules while the core processor is an improvement of the previous high speed reconfigurable hardware architecture therefore, the fuzzy inference speed is increased. Moreover it will have 8-16 inputs and one or two outputs.