Optimization of copper pillar bump design for fine pitch flip-chip packages

In this paper we present new approaches in the development of flip chip technology. We assess the challenges presented by micro bump interconnection. In order to study that we have evaluated different bump designs of stagger 50 um pitch using different flip-chip packages methods Mold Under-filling (MUF) & Capillary Under-filling (CUF). (Figure 1) Finally this paper will conclude by identifying the most robust Cu pillar bump design for fine pitch FCCSP devices.