Implementing extreme upsampling filters with a multiply-less architecture

For ease of implementation, communications systems have been steadily converted to digital implementations. FPGA technologies and high-quality, high-speed DACs have enabled this trend. While this is commonly done for modern high bit-rate communications systems, legacy systems like the MIL-STD-188-165A modem are not often considered. One issue is the need to up-sample these slower standards by factors of tens of thousands in order to interface them with the modulation system. This paper presents an architectural case study on the implementation of a direct digital synthesis MIL-STD-188-165A modem. It briefly describes a multiply-less single stage filter architecture with unlimited up-sampling capabilities. The filter implements a Farrow type design. By selecting the appropriate filter coefficients from a set of look-up-tables (LUT) the filter can be designed to suppress harmonic distortion below the required filter mask. Mathematical evaluation of these properties proves that a reasonable size LUT of 1024×14 bits is sufficient to suppress harmonics below - 60 dB. A full analysis of harmonic suppression vs. LUT size is included to extend this work beyond the MIL-STD-188-165A case study.