Fabrication approach for lateral InGaAs tunnel transistors

In this work, the lateral InGaAs tunnel FET is configured and sized to enable gate control of the Zener (reverse bias) tunneling current. The p+InGaAs transistor channel is 4 nm thick with a n+p+ source injector and a thin 3/3 nm HfO
₂
/Al
₂
O
₃
high-k gate dielectric. Atomic-layer deposition (ALD) is used to deposit the gate dielectric.