Source/drain design for 16 nm surrounding gate MOSFETs

In this paper, we investigate an optimized S/D design for gate structures that had been reported for a 16 nm MOSFET. The high-k surrounding MOSFET is found to achieve comparable delay to the conventional gate structure, but the minimum delay is obtained with an underlap S/D, which is in contrary to the conventional one with an overlap S/D. It is also found that more underlap is preferred for the high-k surrounding gate MOSFET as the permittivity of the gate dielectric layer increases.