Tutorial 2: Queue Machines: An Unknown Alternative

In a world dominated by register (i.e. CISC, RISC) and stack machines (i.e. Java), don't be surprised if you have never heard of queue machines. Nevertheless, queue-based processors offer high instruction-level parallelism, a compact instruction set, simple hardware, and low power consumption. Queue machines are the "parallel siblings" of stack machines. The register file is organized as a first-in first-out (FIFO) queue that decouples reads and writes in benefit of program parallelism and hardware simplicity. Instructions read their source operands from the head of the queue and write their destination operand through the tail of the queue. Given this configuration, novel compilation techniques were needed and we implemented them in the queue compiler infrastructure. During this tutorial, I will guide you from the basic principles of queue computing to the advanced compilation techniques. We will present experimental data that highlights the good characteristics of queue machines as a competitive computer architecture for general purpose computing, embedded systems, streaming applications, and software virtual machines. This tutorial aims at informing the community about a viable alternative for future computer systems based on queue-machines.