Abstract:
Statistical full-chip leakage analysis considering spatial correlation is highly expensive due to its O(N2) complexity for logic circuits with N gates. Although efforts h...Show MoreMetadata
Abstract:
Statistical full-chip leakage analysis considering spatial correlation is highly expensive due to its O(N2) complexity for logic circuits with N gates. Although efforts have been made to reduce the cost at the loss of accuracy, existing methods are still unsuitable for large-scale problems. In this paper we resolve the problem by re-formulating the computation to one that can be done efficiently using a well-developed technique that has been widely used in fast EM simulation and machine learning areas. The resulting algorithm is provably of O(N) or O(N log N) complexity with well-defined and easily-controlled error bounds. Experiments show that using the proposed method it is feasible to handle million-gate circuits within only a few minutes on a regular desktop PC. The corresponding error is less than 0.5% compared to exhausted computation that takes more than 3 days. The proposed method is about 300× faster and 10× more accurate compared to existing grid-approximation method.
Published in: 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers
Date of Conference: 02-05 November 2009
Date Added to IEEE Xplore: 28 December 2009
CD:978-1-60558-800-1
ISSN Information:
Conference Location: San Jose, CA, USA