Improved EEPROM tunnel- and gate-oxide quality by integration of a low-temperature pre-tunnel-oxide RCA SC-1 clean

The effects of integration of a low-temperature RCA standard clean-1 (SC1) on the tunnel- and gate-oxide charge-to-breakdown (Q/sub BD/) and voltage ramped dielectric breakdown (VRDB) distribution in a 0.7 /spl mu/m CMOS EEPROM process technology were studied. A low-temperature (<65/spl deg/C) SC1 used to clean the wafer surface prior to tunnel oxidation resulted in a significantly higher tunnel-oxide Q/sub BD/, as well as improved gate-oxide Q/sub BD/ and mode-B failure rates compared to that for a traditional high temperature (>80/spl deg/C) SC1. The reduced silicon diode etchrate of the low-temperature SC1 allowed for additional gate-oxide annealing during the gate oxidation cycle, while keeping the overall thermal budget (Dt)/sup 1/2/ for the technology equivalent to that with the higher temperature SC1. This resulted in improved gate-oxide VRDB distributions and QED values on large capacitor structures. The tunnel-oxide QBD improvement was most likely due to reduced surface roughness in the tunnel-oxide window regions with the lower temperature SC1. The process including the low-temperature SC1 was also proven to provide equivalent yield to the process with the high temperature SC1 on a 0.7 /spl mu/m, 7 nS 128 macrocell EEPROM programmable logic device.