A model for radial yield degradation as a function of chip size

Yield data was collected from a total of 928 200-mm silicon wafers which were processed using a 1 /spl mu/m CMOS technology. Each wafer was patterned with one of four chips varying in area from 17 mm/sup 2/ to 132 mm/sup 2/. Wafers with like chips were binned together into a single grand composite wafer for each of the four chip sizes. The yield was subsequently plotted as a function of radius, and a mathematical expression was empirically fitted to the radial yield plots. The coefficients from each of the fitted expressions were then used to form a generalized expression for radial yield degradation as a function of chip size. The method of normalization, and the algorithm used to generate the radial yield plots are discussed. An explanation of the data is offered based on geometrical considerations. The radial yield dependence is then incorporated into more traditional yield models.