A LDPC decoder with all single port memories

This paper proposes one LDPC decoder with all single port memories to lower requirements of logic and interconnection and save hardware cost. Considering the lower read-write speed of single port memories than that of dual port memories, the decoder needs to reduce computation complex and shorten the critical path delay so as to get high throughput. To get the purpose, the LDPC decoder uses TDMP algorithm and normalized MS algorithm to reduce computation complex, uses reusable and configurable CVPU to realize single cycle pipeline variable and check node updating calculation, uses optimized shuffle network to shorten the path delay, and uses memories dominated controller to avoid the read and write conflict of memories. The implementation results show for once iteration process the throughputs are about 890 Mbps, 847 Mbps, and 863 Mbps for rate 0.4, 0.6, and 0.8 respectively.