A test structure for the measurement of planarisation

This paper presents simulations of a test structure that can be used to assess the degree of planarisation of inter-layer dielectrics. It consists of sets of comb structures separated by a dielectric. For each structure the combs on the two layers overlap each other with adjacent structures having the overlap in one direction progressionally offset by 0.2 /spl mu/m. The capacitance of these structures is then measured from which the degree of planarisation can be assessed. This structure has potential applications for characterising Chemical Mechanical Polishing (CMP) processes for multi-level VLSI applications.