Use of test structures for a wafer-level-reliability monitoring

To fulfil future quality requirements, the waferfabs need a fast feedback of reliability data additionally to that already established for yield data. Wafer-level-reliability programs for test structures with highly accelerated stress are necessary to reach very short test periods. A concept with a variable drop-in test chip is described. By means of two examples, gate oxide integrity and electromigration, challenges and solutions are presented. The charge to breakdown distribution offers a way to characterize early failures rapidly. The EM test on wafer level allows life time predictions to remain useful.