LFSR based fast seed selection technique reducing test time of IDDQ testing

This paper proposed iddq testing of combinational circuit using linear feedback shift register (LFSR) based fast seed selection technique. Although I
_DDQ
testing is known to be effective to detect faults in CMOS circuit, test time of I
_DDQ
testing is larger than that of logic testing. To reduce test time of I
_DDQ
testing, bit-flipping technique is integrated with LFSR to reduce lower to higher (L to H) switching activities for combinational circuits. Experimental results for ISCAS'85 and ISCAS'89 benchmark circuits show the effectiveness (7% improvement) of the technique for reducing testing time delay.