Parametric test engineering optimization: methodology and software system

To improve drastically the productivity and the quality of parametric testing, we have defined a new design methodology based on a global and concurrent approach. A CAD system has been developed allowing the automatic generation of all the parametric test tools and the secured transfer of all information about the test chip to the parametric tester. This CAD solution has been progressively implemented in the Centre Commun CNET SGS-Thomson to design the test chips for CMOS 0.5 /spl mu/m, CMOS 0.35 /spl mu/m and BiCMOS technologies. Global indicators confirm the productivity and quality improvement of the parametric test design process.