Ni-based self-aligned silicidation (SAS) process on source and drain for planar polysilicon TFT low-voltage flash memory cell

High-density nonvolatile memory applications can benefit tremendously from three-dimensional (3D) integration wi th low power co nsumption. Among several proposals
^[1–4]
, the salicided source an d drain planar polysilicon thin-film transistor (TFT) with metal nanocrystals (NCs) and high-k gate-stack is one of the promising candidates. The self-aligned silicidation (SAS) process is often used to reduce the source, drain and gate resistances of submicron logic MOSFET
^[3–4]
. Especially, N iSi has be en proposed as a suit able silicide for S AS process due to its low resistivity, low formation temperature, and the ext ended thermal stability range
^[3]
. Furthermore, since Ni consumes the least amount of polysilicon to form a given thickness of silicide (NiSi), it has the advantage of utrathin polysilicon layers on insulator substrates. Metal NCs were also introduced to allow thin tunnel di electric, lower the program/erase (P/E) voltage and enhance the cycle en durance
^[5]
. Moreover, reduced low contact resistance by Ni-based SAS process leads t o improved device characteristics and reliable process integration.