A 2.4 GOPS data-driven reconfigurable multiprocessor IC for DSP

Existing hardware prototyping platforms, often based on commercial processors or FPGAs, cannot cope with the high computation requirements of complex DSP algorithms, especially those with high sampling rate and heterogeneous data-now patterns. The multiprocessor IC presented here is designed to handle these types of algorithms. The chip presented here contains 48 16 b PEs interconnected by a 2-level high bandwidth communication network.