Discrete-time full and reduced order anti-windup compensator synthesis for constraint cascade control systems: An LMI based approach

In this paper, discrete-time full and reduced order anti-windup design for general linear cascade control systems under actuator saturation constraint is considered. Based on decoupled architecture with multi-loop compensation, l
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gain reduction, discrete-time Block Diagonal Quadratic Lyapunov Function, and sector bounded-ness, LMI conditions are developed for full and reduced order anti-windup design which guarantees the stability and performance of overall closed-loop system. Results are demonstrated through a simulation example from process control.