Low-power MCML circuit with sleep-transistor

This paper proposes a low-power MOS current mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16×16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MOS current model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 ¿m CMOS process. The validity and effectiveness are verified through the HSPICE simulation.