A parallel-amplification parallel-summation logarithmic amplifier for UHF RFID reader

This paper describes a four gain paths parallel-amplification parallel-summation logarithmic amplifier (PPLA). It is used in the UHF RFID Reader as a part of the ASK demodulating system to compress the high dynamic range input signal. Compared with the successive detection logarithmic amplifier (SDLA), the PPLA has wider bandwidth, and is easier to meet requirement of the system stability. The presented PPLA is implemented in IBM 0.18 ¿m CMOS technology with dynamic range of 70 dB, bandwidth of 1 MHz, and power dissipation of 19 mW.